Discussion:
PEBS support in hwpmc
Bret Ketchum
2017-10-20 11:27:55 UTC
Permalink
All,

I apologize if there is a better forum for this question. Is there
any current effort to support Processor Event Based Sampling in hwpmc?
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best. I'm thinking to simply add a
flag and either add a char to iap_event_descr or increase the size of
iap_evcode to house the sub-event (EVTSEL). Decoding and reporting the
captured PEBS records would need a bit more thought.

Bret
Ryan Stone
2017-10-20 14:24:35 UTC
Permalink
Post by Bret Ketchum
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best
I'm afraid that I don't know of any work related to PEBS in hwpmc.
However, I'm curious as to why PEBS is so important on these
architectures. My experience with hwpmc profiling has been that
callchain information is frequently critical for understanding the
performance characteristics and my understanding is that PEBS by
design cannot capture that information.
Bjoern A. Zeeb
2017-10-20 14:40:21 UTC
Permalink
Post by Ryan Stone
Post by Bret Ketchum
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best
I'm afraid that I don't know of any work related to PEBS in hwpmc.
However, I'm curious as to why PEBS is so important on these
architectures. My experience with hwpmc profiling has been that
callchain information is frequently critical for understanding the
performance characteristics and my understanding is that PEBS by
design cannot capture that information.
Ruslan is working on Intel PT to my best knowledge. Cc:ing him so he
can chime in.

/bz
Bret Ketchum
2017-10-20 16:31:16 UTC
Permalink
PEBS records do capture callchain-like infromation. I'm most
interested (currently) with FRONTEND_RETIRED, MEM_LOAD_RETIRED and
MEM_LOAD_L3_HIT_RETIRED. Which require understanding of sub-events.
These counters can be used to differentiate the myriad of
Front-End/Back-End bound issues before drilling down to offending code
fragments.
Post by Ryan Stone
Post by Bret Ketchum
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best
I'm afraid that I don't know of any work related to PEBS in hwpmc.
However, I'm curious as to why PEBS is so important on these
architectures. My experience with hwpmc profiling has been that
callchain information is frequently critical for understanding the
performance characteristics and my understanding is that PEBS by
design cannot capture that information.
Ruslan Bukin
2017-10-20 15:50:04 UTC
Permalink
I have not seen that yet. We are working on Intel PT support currently.
But we plan to look at ARM v8.2 Statistical Profiling Extension technology too, which sounds similar to PEBS by Intel ?

Ruslan
Post by Bret Ketchum
All,
I apologize if there is a better forum for this question. Is there
any current effort to support Processor Event Based Sampling in hwpmc?
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best. I'm thinking to simply add a
flag and either add a char to iap_event_descr or increase the size of
iap_evcode to house the sub-event (EVTSEL). Decoding and reporting the
captured PEBS records would need a bit more thought.
Bret
_______________________________________________
https://lists.freebsd.org/mailman/listinfo/freebsd-arch
Bret Ketchum
2017-10-20 16:36:26 UTC
Permalink
Looks like PT would assist in instruction execution performance
analysis. PEBS provide information related to uops flows in the OOO
pipeline including cache operations, prefetch, etc.

On Fri, Oct 20, 2017 at 10:50 AM, Ruslan Bukin
Post by Ruslan Bukin
I have not seen that yet. We are working on Intel PT support currently.
But we plan to look at ARM v8.2 Statistical Profiling Extension technology too, which sounds similar to PEBS by Intel ?
Ruslan
Post by Bret Ketchum
All,
I apologize if there is a better forum for this question. Is there
any current effort to support Processor Event Based Sampling in hwpmc?
Without this support (or a VTune subscription) understanding
Front-End/Back-End bound applications running on Skylake/Kaby Lake
processors will be difficult at best. I'm thinking to simply add a
flag and either add a char to iap_event_descr or increase the size of
iap_evcode to house the sub-event (EVTSEL). Decoding and reporting the
captured PEBS records would need a bit more thought.
Bret
_______________________________________________
https://lists.freebsd.org/mailman/listinfo/freebsd-arch
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